A Methodology to Design FPGA-based PID Controllers

This paper presents a methodology to implement PID (Proportional, Integral, Derivative) controllers in FPGAs (Field-Programmable Gate Arrays) using fixed-point numerical representation. The Matlab/Simulink environment is used for modeling, simulation and evaluation the performance provided by different fixed-point representations using a given control process. A static bit-width analyzer is used to give a specialized fixed-point representation for each operand/operator in the controller system. After bit-width analysis, a VHDL represen-tation of the system is generated. Results show that the proposed methodology leads to shorten design cycles achieving important resource savings by employing specialized fixed-point repre-sentations

Implementation of an Ethernet 10/100Mbps core with Avalon interface for Nios II processor from Altera

O presente trabalho apresenta a implementação de um core de rede Ethernet 10/100Mbps com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. A tecnologia Ethernet foi implementada em computação reconfigurável e utilizou-se como base um módulo disponível na Internet denominado OpenCores MAC 10/100. O projeto foi desenvolvido para ser aplicado em sistemas embarcados, mais especificamente para o uso em um robô móvel em desenvolvimento no Laboratório de Computação Reconfigurável do ICMC/USP. O core foi incorporado à biblioteca da ferramenta SoPC Builder da Altera, visando uma fácil integração do mesmo em outros projetos. Foram utilizadas as ferramentas Quartus II e ModelSim para o desenvolvimento e testes do sistema, além de dois kits Nios versão Stratix para a validação do projeto, sendo as placas interligadas ponto-a-ponto sem a utilizaçao de transceivers analógicos.This work presents the implementation of a network Ethernet 10/100Mbps core with interfaces to Avalon bus for using with the Nios II processor from Altera. The Ethernet technology was implemented in reconfigurable computing and was based in the OpenCores MAC 10/100 available on Internet. The project was developed for embedded systems applications, more specifically for a mobile robot in development at Reconfigurable Computing Laboratory from ICMC/USP. The core was incorporated to SoPC Builder tools library from Altera, aiming to facilitate the integration with others projects. To development and system tests were used Quartus II and ModelSim, and two Nios Development kit Statix Edition for project validation. The boards were linked peer-to-peer, without use analog transceivers

LALP: a language for parallelism of loops exploitation in reconfigurable computing

A computação reconfigurável tem se tornado cada vez mais importante em sistemas computacionais embarcados e de alto desempenho. Ela permite níveis de desempenho próximos aos obtidos com circuitos integrados de aplicação específica (ASIC), enquanto ainda mantém flexibilidade de projeto e implementação. No entanto, para programar eficientemente os dispositivos, é necessária experiência em desenvolvimento e domínio de linguagem de descrição de hardware (HDL), tais como VHDL ou Verilog. As técnicas empregadas na compilação em alto nível (por exemplo, a partir de programas em C) ainda possuem muitos pontos em aberto a serem resolvidos antes que se possa obter resultados eficientes. Muitos esforços em se obter um mapeamento direto de algoritmos em hardware se concentram em loops, uma vez que eles representam as regiões computacionalmente mais intensivas de muitos programas. Uma técnica particularmente útil para isto é a de loop pipelining, a qual geralmente é adaptada de técnicas de software pipelining. A aplicação dessas técnicas está fortemente relacionada ao escalonamento das instruções, o que frequentemente impede o uso otimizado dos recursos presentes nos FPGAs modernos. Esta tese descreve uma abordagem alternativa para o mapeamento direto de loops descritos em uma linguagem de alto nível para FPGAs. Diferentemente de outras abordagens, esta técnica não é proveniente das técnicas de software pipelining. Nas arquiteturas obtidas o controle das operações é distribuído, tornando desnecessária uma máquina de estados finitos para controlar a ordem das operações, o que permitiu a obtenção de implementações eficientes. A especificação de um bloco de hardware é feita por meio de uma linguagem de domínio específico (LALP), especialmente concebida para suportar a aplicação das técnicas. Embora a sintaxe da linguagem lembre C, ela contém certas construções que permitem intervenções do programador para garantir ou relaxar dependências de dados, conforme necessário, e assim otimizar o desempenho do hardware geradoReconfigurable computing is becoming increasingly important in embedded and high-performance computing systems. It allows performance levels close to the ones obtained with Application-Specific Integrated circuits (ASIC), while still keeping design and implementation flexibility. However, to efficiently program devices, one needs the expertise of hardware developers in order master hardware description languages (HDL) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Many efforts trying to achieve a direct of algorithms into hardware concentrate on loops since they represent the most computationally intensive regions of many application codes. A particularly useful technique for this purpose is loop pipelining, which is usually adapted from software pipelining techniques. The application of this technique is strongly related to instruction scheduling, whic often prevents an optimized use of the resources present in modern FPGAs. This thesis decribes an alternative approach to direct mapping loops described in high-level labguages onto FPGAs. Different from oyher approaches, this technique does not inherit from software pipelining techniques. The control is distributed over operations, thus a finite state machine is not necessary to control the order of operations, allowing efficient harware implementations. The specification of a hardware block is done by means of LALP, a domain specific language specially designed to help the application of the techniques. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardwar

LALP: a language to program custom FPGA-based acceleration engines

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained with Application-Specific Integrated Circuits, while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers in order to master hardware description languages (HDLs) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Bearing in mind an FPGA available resources, it has been developed LALP (Language for Aggressive Loop Pipelining), a novel language to program FPGA-based accelerators, and its compilation framework, including mapping capabilities. The main ideas behind LALP are to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to allow the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. Those features are particularly useful to implement loop pipelining, a well regarded technique used to accelerate computations in several application domains. This paper describes LALP, and shows how it can be used to achieve high-performance computing solutions.CNPq/GricesFAPESP [573963/2008-8, 08/57870-9]FCT, Portugal [PTDC/EEA-ELC/70272/2006]CNP

Dry Climate as a Predictor of Chagas’ Disease Irregular Clusters: A Covariate Study

ovariate studies associating the presence of regularly shaped geographic clusters with environmental factors are routinely done using the Circular Scan.  However, if the study employs irregular clusters instead, accurate results depend on the generation of a rich family of variants of the primary cluster.  We employ climate information to assess the possible spatial dependence on the occurrence of Chagas' disease irregular clusters in Central Brazil, using a modification of the Spatial Scan Statistic, the Geo-Dynamic Scan.  It finds more potentially useful variants of the primary cluster with more desirable covariate values.  This information could be useful in Chagas' disease surveillance

Multi-objective dynamic programming for spatial cluster detection.

The detection and inference of arbitrarily shaped spatial clusters in aggregated geographical areas is described here as a multi-objective combinatorial optimization problem. A multi-objective dynamic programming algorithm, the Geo Dynamic Scan, is proposed for this formulation, finding a collection of Pareto-optimal solutions. It takes into account the geographical proximity between areas, thus allowing a disconnected subset of aggregated areas to be included in the efficient solutions set. It is shown that the collection of efficient solutions generated by this approach contains all the solutions maximizing the spatial scan statistic. The plurality of the efficient solutions set is potentially useful to analyze variations of the most likely cluster and to investigate covariates. Numerical simulations are conducted to evaluate the algorithm. A study case with Chagas’ disease clusters in Brazil is presented, with covariate analysis showing strong correlation of disease occurrence with environmental data

[Lectura de poesías brasileñas]‎ : 11-05-1959

Guilherme de Almeida. Olegário Mariano‎. Álvaro Moreyra. Frederico Schmidt. Abgar Renault. Cassiano Ricardo. Adalgisa Nery. Cecilia Meireles . Sergio Milliet. Manuel Bandeira. Gilberto Amado. Rosalina Coelho. Joao Cabral. Menotti del Picchia. Emilio MouraMadrid, Instituto de Cultra Hispánica. Martes, 11 de mayo a las siete y media de la tardeCinta 1: Guilherme de Almeida lee, “Carta a mina noiva” – Min. 10.05: Olegario Mariano lee, “O homem da noite”, “A velha estrada”, “Paisagem natal”, “Ao calor da lareira”, “Tu ficaras” -- Cinta 2: Álvaro Moreyra lee, “Oraçao”, “Minha mae”, “Minha dor”, “Cançao de realejo”, “Amor”, “Projeto”, “Bem”, “Ventagem”, “Oraçao de Santo Antonio”, “Cançao”, “Tema” – Min. 11.16: Frederico Schmidt lee, “Morte da india”, “Quando”, “Núpcia nº2”, “Noiva”, “Os príncipes”, “Historia da borboleta branca”, “O pássaro”, “Soneto” – Min. 25.16: Abgar Renault lee, “Última thule”, “Claro e oscuro”, “O camino espera” -- Cinta 3: Cassiano Ricardo recita, “Ode pastoril”, “Os parequedistas”, “A flauta que me roubaron”, “Plano inclinado”, “O cacto” – Min. 11.18: Adalgisa Nery lee, “A consentida”, “Ensinamentos”, “Poema da amante”, “Carta de amor”, “Eu te amo”, “Repouso”, “A mulher triste”, “Força” – Min. 21.42: Cecilia Meireles recita, “A presentaçao”, “Retrato”, “Elegía a una pequena borboleta”, “Guitarra”, “Cabalo morto”, “Balada das dez bailarinas du casino”, “Romance da bandeira da inconfidencia” -- Cinta 4: Abgar Renault recita, “Como quem pede uma esmola”, “Manha” – Min. 04.27: Sergio Milliet lee, “Paisagen italiana”, “Longitudes”, “Que nada recordé nada”, “O morto”, “Bem da gente”, “O mar outropa”, “Lembrança”, “Tristeza”, “Vazio”, “Sob o signo da virgen”, “Inverno suiço” – Min. 14.36: Manuel Bandeira lee, “A chave do poema”, “Berimbau”, “O cacto”, “Pneumotorax”, “Namorados”, “Estrela da manha”, “Piscina”, “A ninfa” – Min. 24.35: Gilberto Amado recita, “A vida e artista”, “Melancolía”, “Triste vangloria”, “Dançarina” -- Cinta 5: Gilberto Amado recita, “Nenhuma”, “Predestinaçao”, Última brasa” -- Min. 03.48: Rosalina Coelho lee, “Experiencia”, “Caminho”, “Súplica”, “Heroi”, “Inconsciencia”, “Minha mae” – Min. 14.53: Murilho Mendes lee, “Jandira”, “A sesta”, “Metafísica da moda”, “Metade passaro”, “Poema barroco”, “A marcha da historia”, “A ceia siniestra”, “Pastoral” – Min. 26.27: Joao Cabral recita, “Pregón turístico de Recife”, “O vento no canavial”, “Valle do Capibarive” -- Cinta 6: Joao Cabral lee, “Cementerio de Torotima”, “Cementerio de San Lorenzo da Mata”, “Cementerio de Nuestra Señora de la Luz”, “Volta a Pernambuco”, “Alto do Trappua” – Min. 07.11: Menotti del Picchio recita, “Cançao de meu sonho errante”, “O clásico soneto”, “Senhora do Manto de Treva”, “Máscaras”, “Soneto”, “Cantiga do amor temporao”, “A voz das coisas” – Min. 19.36: Emilio Moura recita, “Soneto”, “Tal vez”, “Como a noite descese”, “Palabras a Isaias”, “Tres caminos”, “Poema”, “Viagem